1. Field of the Invention
The present invention relates to a multilayered structure in which insulating layers and electrode layers are alternately stacked, a multilayered structure array in which plural multilayered structures are arranged, and a method of manufacturing the multilayered structure or the multilayered structure array.
2. Description of a Related Art
Multilayered structures, in each of which insulating (dielectric) layers and electrode layers are alternately formed, are utilized not only for multilayered capacitors but also for various uses such as piezoelectric pumps, piezoelectric actuators, and ultrasonic transducers. In recent years, with the developments of MEMS (micro electro mechanical systems) related devices, elements each having such a multilayered structure have been microfabricated still further and packaged more densely.
In microfabrication of an element having opposed electrodes, since the smaller the area of the element is made, the smaller the capacity between the electrodes becomes, a problem that the electrical impedance of the element rises occurs. For example, when the electrical impedance rises in a piezoelectric actuator, the impedance matching cannot be taken with a signal circuit for driving the piezoelectric actuator and power becomes difficult to be supplied, and thereby, the performance as the piezoelectric actuator is degraded. Alternatively, in an ultrasonic transducer using a piezoelectric element, oscillation intensity of ultrasonic wave is dropped. Accordingly, in order to enlarge the capacity between electrodes while microfabricating the element, plural piezoelectric material layers and plural electrode layers are alternatively stacked. This is because the capacity between electrodes of the entire element can be made larger by connecting the stacked plural layers in parallel.
In such a multilayered structure, in order to connect the plural internal electrode layers to one another, interconnection is performed on the side surfaces of the multilayered structure. FIG. 15 is a sectional view for explanation of a general interconnection method of a multilayered structure. The multilayered structure 100 includes plural piezoelectric material layers 101, plural internal electrode layers 102 and 103, and two side electrodes 104 and 105. The internal electrode layers 102 are formed such that one end thereof may extend to one wall surface of the multilayered structure and connected to the side electrode 104 and insulated from the side electrode 105. Further, the internal electrode layers 103 are formed such that one end thereof may extend to the other wall surface of the multilayered structure and connected to the side electrode 105 and insulated from the side electrode 104. By applying a potential difference between the side electrode 104 and the side electrode 105, an electric field is applied to the piezoelectric material layers 101 disposed between the internal electrode layers 102 and the internal electrode layers 103, and the piezoelectric material layers 101 expand and contract by the piezoelectric effect.
By the way, as shown in FIG. 15, in the layers in which the internal electrode layers 102 and 103 are disposed, insulating regions 106 in which no electrode is formed are provided for insulating the electrode layers from either of the side electrodes. The insulating regions 106 do not expand or contract even when a voltage is applied to the multilayered structure 100. On this account, there is a problem that stress is concentrated on the part and the part becomes easy to break.
A multilayered structure shown in FIG. 16 is known as one using another interconnection method in the multilayered structure. The multilayered structure 200 shown in FIG. 16 has plural piezoelectric material layers 201, plural internal electrode layers 202, insulating films 203 formed on one end surfaces of the respective internal electrode layers 202, and two side electrodes 204 and 205. In the adjacent two internal electrode layers 202, the end surfaces on the opposite sides are covered by the insulating films 203 and the layers are insulated from either one of the side electrodes 204 and 205, and thereby, a circuit equivalent to the multilayered structure 100 shown in FIG. 15 can be realized.
As shown in FIG. 16, in the multilayered structure 200, since the internal electrode layers 202 are formed over the entire surfaces of the piezoelectric material layers 201, the multilayered structure 200 is more advantageous than the multilayered structure 100 shown in FIG. 15 in expression of piezoelectric performance. Further, as described above, since the stress concentration as in the insulating regions 106 (FIG. 15) is not generated in the multilayered structure 200, the life of multilayered structure hardly becomes shorter.
However, in order to fabricate the multilayered structure 200, the insulating films 203 should be formed on every other end surface of the internal electrode layer 202 exposed at each side surface of the multilayered structure 200. Currently, the insulating films 203 is often formed by using brushing, printing, or photolithography technology, and there is a problem that the productivity is low according to those methods. Further, it is very difficult according to those methods to form insulating films on a two-dimensional array in which plural multilayered structures are arranged with narrow pitches. As another method, as disclosed in Japanese Patent Examined Application Publication JP-B2-61-32835, on exposed side end surfaces of internal electrode layer plates of electrostriction effect elements, the insulating layers are formed by electrophoresis only on the exposed parts of the internal electrode layer plates and the electrostriction materials nearby. In JP-B2-61-32835, glass is used as a material of the insulting layers. However, glass films formed by electrophoresis are aggregates of cluster particles, and they are sparse films. Accordingly, in order to obtain a sufficient withstand voltage, the thickness of the insulating layer is required to be several tens of microns. However, in the case where an ultrasonic transducer array is fabricated, it becomes a problem that ultrasonic transducers cannot be laid out with narrow pitches due to such thickness of the insulating layer.